1. Technical Field
The present invention relates generally to an improved apparatus and method for noise reduction in multi-layered packages. More specifically, the present invention is directed to an apparatus and method for far end noise reduction in multi-layered ceramic packages using capacitive cancellation by offset wiring.
2. Description of Related Art
As Very Large Semiconductor Integrated (VLSI) circuits become more dense, there is a need in the art to have semiconductor packaging structures that can take full advantage of the density and speed provided by state of the art VLSI devices. Present day modules made of ceramic, typically multilayered ceramic modules, are normally mounted onto cards or boards, with cards or boards combined together to form the central processing unit (CPU) of a computer. The multilayer ceramic (MLC) modules typically have VLSI chips mounted on the top surface.
Multilayer modules are used for the packaging of electronic components, especially integrated circuit chips. Both single chip modules (SCM) and multi chip modules (MCM) are widely used. The most common type of such modules is the multilayer ceramic packaging module. In this type of module, the layers consist of a ceramic or glass-ceramic material. However, other types of thick film technologies are known, such as glass epoxy and Teflon. An example of multilayer ceramic packages is provided in U.S. Pat. No. 5,812,380, issued to Frech et al. on Sep. 22, 1998, which is hereby incorporated by reference.
As integrated circuit speeds and packaging densities increase, the importance of the packaging technology becomes increasingly significant. For example, as devices approach gigahertz speed, inductance effects in the package become more significant. Such inductance effects may arise from switching, for example, and are particularly problematic in power and ground leads. Inductance effects in the package can cause ground bounce, signal cross-talk and the like. Increasing circuit size and speed also impact the heat dissipation ability of the package.
VLSI and Ultra Large Semiconductor Integrated (ULSI) chips are especially designed for high performance applications and are thus limited by noise. The noise is caused by a high number of simultaneously switching off-chip drivers (OCD noise) and by a high number of simultaneously switching latches and the associated logic gates (logic noise). Both noise sources impact and restrict the on-chip and off-chip performance and jeopardize the signal integrity. Both noise sources generate noise due to line-to-line coupling and due to the collapse of the voltage-ground (GND) system.
The wiring layers in a typical multi-layer ceramic package are designed in a stacked tri-plate configuration with the signal wiring being sandwiched between upper and lower reference planes (typically alternating in voltage and ground polarity). These reference planes are meshed in a regular grid structure to allow via interconnections for the signal and power lines. This tri-plate structure is a controlled impedance environment that allows high speed signal propagation.
With increased signal rising and falling edge rates and bus signaling speeds, signals on these wiring layers interact with other signals on the signal layers above and below it through the meshed reference structure. This interaction, i.e. cross-talk, between high speed signals introduces inter-symbol interference (ISI) on the nets that severely limits the maximum signaling rates and performance on these nets. ISI is the distortion of a received signal, wherein the distortion is manifested in the temporal spreading and consequent overlap of individual pulses to the degree that the receiver cannot reliably distinguish between changes of state, i.e. between individual signal elements. At a certain threshold, inter-symbol interference will compromise the integrity of the received data.